Continued developments in integrated circuit (IC) design, fabrication and packaging has afforded ever denser and faster circuits. Indeed, developments in complimentary metal-oxide semiconductor (CMOS) technologies have allowed digital circuits to implement functionality that was once only achievable through purely analog circuits. By way of high-performance CMOS processes, such modulation may be performed entirely in the digital domain, including the final tuning.
Converting a digitally modulated signal into a corresponding modulated analog signal typically requires a digital-to-analog converter (DAC) that can perform signal conversions at a very high sampling rate so that spectral replicas are removed from the desired spectral band of the reconstructed signal. Practically, such high sampling rate is easy to achieve on the DAC, which allows a reduction sample resolution for a given signal-to-noise ratio (SNR) due to quantization noise spreading (oversampling). This reduced resolution simplifies the analog design and improves its performance, e.g., for a given area and power, bigger devices with better matching can be used, improving the overall linearity.
The ability of the modulator to support multiple output carrier frequencies from an arbitrary clock source is considered advantageous, often a must have, in that the clock frequency is very likely to be constrained by other factors. Multiple modulation frequencies have, in the past, been achieved by a fractional-N synthesizer and a sample rate converter. A classical solution consists in clocking the DAC at four times the carrier frequency resulting in a very simple digital sequence (1,1, −1, −1) for the oscillator signal by which the carrier modulation is achieved. However, the need has been felt for modulation techniques by which an information-bearing signal may be digitally modulated by a signal that is independent of the clock frequency while avoiding the use of multiple asynchronous clocks.